The semiconductor industry has undergone a fundamental shift over the past year, and it’s one that will redefine chipmaking over the next decade or more.While the focus is still on building the fastest, lowest-power devices, whether that’s by shrinking features or packaging them into blazing-fast 2.5D or fan-out configurations, these devices are being customized for specific use cases much more than in the past. At the introduction of Moore’s Law, and even in the foundation development years before that, the big challenge was to put electronic devices together and make sure they would work. CPU ASICs were the stars, and everything else was of lesser importance. Memory was a commodity. I/O was a wire. And that basically summed up the von Neumann architecture. You could use it to build a faster computer, but you couldn’t do much else with it.Fast forward to 2017 and the tech world has changed rather significantly. And while it’s true that these technologies … [Read more...] about Preparing For Bigger Changes Ahead
By Ron Press and Vidya NeerkundarThe reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability. With more DFT steps, the overall rate of success declines unless the rate of success at each step is extremely high. So, how do you ensure an extremely high rate of success at each step in the DFT flow? By adopting a smarter DFT methodology that includes:Plug-and-play infrastructure to connect and manage the inserted DFT logic, and to manage other design components during test.Automation to improve the reliability of your DFT flows. Any manual steps add risk to the DFT methodology.Customization to facilitate company- specific flows or operations.The best and most widely adopted DFT methodologies … [Read more...] about Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling
Automobiles are undergoing a dramatic transformation. Autonomous vehicles have debuted, and the stakes for safety are now sky-high. Learn how NetSpeed brings performance, sensing, and safety together for ISO 26262 applications with a fully automated, configurable, correct-by-construction approach where a NoC is optimized with its functional safety (FuSa) features. To read more, click here. … [Read more...] about Intelligent Interconnect Blends Performance, Sensing And Safety In Automotive SoCs
We just concluded two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic presented their HBM2 controller solutions. A complete ecosystem to address the requirements of advanced ASICs for markets such as high-performance computing, networking, deep learning and 5G. If you wish you could have been there, read on – there is another chance.So, I feel like I have an unfair advantage to answer the question, “what’s next?” Based on the attendance at our events and the questions the attendees asked, I would say we’ll be seeing a lot more advanced ASICs in 2018 targeting high-performance computing, networking, deep learning and 5G infrastructure. … [Read more...] about What’s Next?
Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM’s prototyping mode accounts for the limitations of the target FPGAs and allows the user to map a design to the FPGAs within these constraints. Partitioning a design to fit into multiple FPGAs can be a lot of workDesigning the partitions with HES-DVM is as easy as selecting specific VHDL/SystemVerilog design modules from the hierarchy and moving them to a desired partition. All information about the design modules and the amount of LUTs, Flip-flops, memory blocks, DSP slices, and I/O consumed are displayed for convenience. These values can also be viewed as a percentage of the target FPGAs’ available … [Read more...] about Partitioning With Ease